The present invention is related to testing of logic circuit designs, in particular in the context of compression of test patterns for logic testing.
Testing of complicated digital logic circuits requires the generation of large test patterns. Unfortunately, the sizes of scan test patterns for today's large designs can be even larger than the sizes of typical tester memory. This necessitates multiple loading of test patterns during a test application and, in turn, increases test application time and test cost. The oversized test pattern set problem is even more severe in delay testing, which has become a necessary test procedure for deep-sub micron chips. Delay test set sizes are often significantly larger than memory capacities of inexpensive testers. Test set sizes and test application times are major factors that determine the test cost of an integrated circuit.
One technique for addressing the issue is to compress the test data. Most prior art test data compression techniques proposed and developed for commercial use achieve compression by storing the seeds of a linear test pattern generator (e.g., such as a linear feedback shift register (LFSR) or a linear hybrid cellular automata (LHCA)) instead of the whole pattern. See B. Köinemann, “LFSR-coded Test Patterns for Scan Designs,” Proc. Of European Test Conf., pp. 237-42 (1991). The test pattern is generated from the seed by first loading the seed and then running the linear test pattern generator for several cycles. The seeds are obtained by solving a system of linear equations. Compression is achieved because many of the bits in the test patterns are, in fact, unspecified (“don't cares”). FIG. 1 shows the architecture of typical reseeding schemes, where the linear test pattern generator is loaded with an m-bit seed by the tester and is then run in autonomous mode to produce an n-bit scan test pattern. The generator can be directly connected to the scan chain in the case of a single scan chain in the design or connected to multiple scan chains using a phase shifter. It has recently been suggested to further compress the seeds of the linear test pattern generator by using statistical coding. See C. V. Krishna and N. A. Touba, “Reducing Test Data Volume Using LFSR Reseeding with Seed Compression,” Proc. International Test Conference, pp. 321-30 (2002). Seeds of the LFSR are chosen such that they can be encoded using a statistical code. Unfortunately, a statistical decoder is dependent on the test set and, if the test pattern set is modified (which may happen due to last minute design changes), the design of the algorithm as well as the statistical decoder need to be changed. It has also been proposed to encode the seeds of the LFSR by the number of clock cycles the LFSR needs to reach the new seed from the current seed. See A. Al-Yamani and E.J. McCluskey, “Seed Encoding with LFSRs and Cellular Automata,” in Proc. Design Automation Conference, pp. 560-65 (2003). The cost of the scheme, however, is the time required to reach the intended seed from the current seed, which for large LFSRs will increase the test application time enormously. The “reseeding” control circuit again depends on the test pattern set.